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Mudasir Shafat Kawoosa

Mudasir Shafat Kawoosa

Senior Design Engineer
Open Silicon
 
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Mudasir Shafat Kawoosa's Experience
ASIC Design Engineer
Open Silicon, Bangalore, INDIA
Project Engineer
Wipro Technologies, Bangalore, INDIA
Mudasir Shafat Kawoosa's Education
M.Tech
Indian Institute of Technology, Madras
PG Diploma
DOEACC Centre, Calicut, Kerala
B.Tech/B.E.
University of Jammu

About Mudasir Shafat Kawoosa's family

I belong to a well educated family. My father is a retired central government employee and my mother as an educationist. I have one elder brother and he is into garment business. He is married happily and has a son as well. I am about to get married and my fiance is pursuing her PhD in Anti-Cancer.
A Fine Balance:
Well It all lies in between you and your family and understanding of job. Work and Life goes side by side and as you progress both adds complicacy as well as enjoyment. As long as you want enjoyment, you need to face hectic schedules but make sure working over entire week demands weekend getaways.
Essential Advice
Build the basics of your engineering clearly and thoroughly because Design For Test in which I am working demands thorough basic knowledge. IN addition to this make sure you understand that you will be working pre-silicon as well as post-silicon activity unlike other VLSI domains viz STA, PD, RTL.
Areas for the Future
DFT is related to RTL STA, PD and Post-Silicon Activity as well as Yield Analysis.All these specializations are equally important.
Required Reading
For DFT I suggest use google and above that VLSI Test Principles and Architectures by Laung.
Degrees that Matter
a PG Diploma in VLSI Design will help you a lot to enter into this domain.
The Journey So Far
BEngg in E&C from MIET Jammu, PG Dip in VLSI from DOEACC Calicut, Project Engg at Wipro, MTech in EE from IIT Madras , ASIC Design Engineer at Open-Silicon India and now Senior Design Engineer at Texas Instruments.
Currently working at
I work as Senior Design Engineer at Texas Inst in Design For Test. My job profile is to ensure add the test design inside chip to ensure the chip is fully testable on ATE at speed.This involves Scan,BIST insertion followed by pattern generation and validation and then post silicon debug.
Tech trends to watch out for
We are moving toward 20nm design and lower which means going to GHz and THz frequency. The silicon size is shrinking day by day but the challenges are heading up more and more to close the design successfully. From career perspective there is lot of growth in this domain.
Role Model
My role model is beloved Prophet Muhammad SAW(Peace be Upon Him). Because I believe your work and life(herein and hereafter) to remain balanced and successful you need to be on right path and successful path which I am sure has been laid down from Allah for us through prophet.
Points of inflection
Begin with completion of my degree,my first job my joining and completing successfully my studies at IIT Madras and career growth continuations at open-silicon as well as Texas.
Plans for the Future
Well Is still consider my self in learning phase and will prefer to be in it for next few years.
Current and Previous Responsibilities
To ensure success of silicon testing.
Most Important Decisions
leaving job and joining studies and then finishing studies and joining back.
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